Method of manufacturing semiconductor device

ABSTRACT

A method of manufacturing a semiconductor device including at least one step of: forming a transistor on and/or over a semiconductor substrate; forming silicide on and/or over a gate electrode and a source/drain region of the transistor; removing an uppermost oxide film from a spacer of the transistor; and forming a contact stop layer on and/or over the entire surface of the substrate including the gate electrode.

The present application claims priority under 35 U.S.C. 119 to KoreanPatent Application No. 10-2006-0092096 (filed on Sep. 22, 2006), whichis hereby incorporated by reference in its entirety.

BACKGROUND

Aspects of semiconductor technology have focused on enhancing theintegration of semiconductor devices (e.g., achieving smaller scaledevices). Reducing channel lengths may serve an important role in thedevelopment of smaller scale semiconductor devices. Reducing channellengths may produce undesirable consequences such as a short channeleffect.

In order to overcome or otherwise suppress the short channel effect,horizontal reduction and vertical reduction may be employed.Particularly, horizontal reduction in a gate electrode width andvertical reduction in the gate insulating thickness and source/drainjunction depth. With horizontal reduction and vertical reduction, anapplied voltage is reduced and a doping density of a semiconductorsubstrate is increased. Particularly, a doping profile of a channelregion can be efficiently controlled.

Although reduction in the size of a semiconductor device can be reduced,the necessary power required for operating an electronic device is high.For example, electrons injected from a source in an NMOS transistor maybe significantly accelerated in a potential gradient state of a drain,thereby the NMOS transistor may become vulnerable to hot carriergeneration. Consequently, a lightly doped drain (LDD) structure may beemployed in order to overcome the hot carrier generation.

As illustrated in example FIG. 1, in a transistor having a LDDstructure, low-concentration n-type region 104 may be located betweenchannel 102 and high-concentration n⁺-type source/drain 106.Low-concentration n-type region 104 drops a high drain voltage near adrain junction to prevent a rapid potential gradient, therebysuppressing hot carrier generation.

In order to achieve high integration in semiconductor devices, a varietyof technologies for manufacturing a MOSFET having a LDD structure hasbeen suggested. An LDD manufacturing method for forming spacer 105 onsidewalls of gate electrode 103 is one such method. While this methodmales it possible to obtain a reduction in channel length, itsshortcomings is that it produces a reduction in charge mobility. Suchreduction in charge mobility causes a reduction in drive current, whichin turn, adversely effects the operability of a semiconductor device.

SUMMARY

Embodiments relate to a method of manufacturing a semiconductor devicecapable of increasing stress applied to a channel of a transistor toenhance charge mobility.

In accordance with embodiments, a method of manufacturing asemiconductor device includes at least one of the following steps.Forming a transistor on and/or over a semiconductor substrate. Formingsilicide on and/or over a gate electrode and a source/drain region ofthe transistor. Removing an uppermost oxide film from a spacer of thetransistor. Forming a contact stop layer on and/or over the entiresurface of the substrate including the gate electrode.

In accordance with embodiments, formation of the transistor may includeat least one of the following steps. Forming a gate insulating film onand/or over the semiconductor substrate. Forming a gate electrode onand/or over the gate insulating film. Forming a lightly doped drain(LDD) region on and/or over the surface of an active region at bothsides of the gate electrode. Forming a spacer having anoxide-nitride-oxide (ONO) structure on both sidewalls of the gateelectrode. Forming the source/drain region on and/or over the surfacesof the substrate at both sides of the gate electrode including thespacer.

In accordance with embodiments, formation of the spacer may include atleast one of the following steps. Sequentially laminating an oxide film,a nitride film and an oxide film on and/or over the entire surface ofthe substrate including the gate electrode. Performing a reactive ionetching process such that an ONO structure remains on both sidewalls ofthe gate electrode.

In accordance with embodiments, the ONO structure may includesequentially laminating from a lower surface of the substrate an oxidefilm having a thickness range of approximately 150 to 200 angstroms, anitride film having a thickness range of approximately 150 to 200angstroms and an oxide film having a thickness range of approximately300 to 500 angstroms.

Preferably, the uppermost oxide film may be removed using a wet etchingprocess, and the wet etching process may be performed using any one of amixed solution of NH₄F and HF and a buffered HF (BHF) solution for 30 to60 seconds. The mixed solution of NH₄F and HF may have a ratio of 30:6.

Preferably, the contact stop layer may be formed using a plasma enhancedchemical vapor deposition (PECVD) method. Here, the PECVD method may beperformed at a temperature of 300 to 500° C. for 30 to 60 seconds underthe condition that bias power is set to 10 to 20 W and a ratio of SiH₄to NH₃ is set to 3:1 to 5:1. In more detail, when an NMOS transistor isformed on the semiconductor substrate, bias power for the PECVD methodmay be set to 10 to 12 W and a ratio of SiH₄ to NH₃ may be set to 5:1such that the contact stop layer has a tensile stress characteristic.Alternatively, when a PMOS transistor is formed on the semiconductorsubstrate, bias power for the PECVD method may be set to 18 to 20 W anda ratio of SiH₄ to NH₃ may be set to 3:1 such that the contact stoplayer has a compressive stress characteristic.

Preferably, the contact stop layer may be formed with a thickness of 300to 500 angstroms.

Preferably, the contact stop layer may be formed of a nitride film.

DRAWINGS

Example FIG. 1 illustrates a method of manufacturing a semiconductordevice.

Example FIGS. 2A to 2E illustrate a method of manufacturing asemiconductor device, in accordance with embodiments.

DESCRIPTION

As illustrated in example FIG. 2A, device isolation film 201 is formedin a field region of semiconductor substrate 200 to define an activeregion in semiconductor substrate 200. Device isolation film 201 may beformed using an isolation process such as shallow trench isolation(STI). Semiconductor substrate 200 may be a conductive n-type or ap-type single crystal silicon substrate.

As illustrated in example FIG. 2B, after formation of device isolationfilm 201, a transistor is formed that may include gate insulating film202, gate electrode 203, lightly doped drain (LDD) region 204, spacer208 including first oxide film 205, nitride film 206 and second oxidefilm 207, and source/drain region 209.

Gate insulating film 202 can be deposited on and/or over the activeregion of semiconductor substrate 200 using a thermal oxidation process.A conductive layer for gate electrode 203 is laminated on gateinsulating film 202. A photoresist pattern for an etching maskcorresponding to a pattern of gate electrode 203 can be formed on and/orover the conductive layer in a region where gate electrode 203 will beformed. The photoresist pattern can be formed using a photolithographicprocess. Thereafter, the conductive layer and gate insulating film 202can be etched until the active region of semiconductor substrate 200 isexposed, while leaving the conductive layer and gate insulating film202. Accordingly, the patterns of gate electrode 203 and gate insulatingfilm 202 can be formed on and/or over a portion of the active region.

Subsequently, LDD region 204 can be formed using a low-concentrationdopant ion implantation process with respect to the entire surface ofsubstrate 200. If the dopant ions are an n-type, arsenic (As) ions maybe used under the condition that energy is in a range betweenapproximately 1 to 3 KeV and a dosage in a range between approximatelyis 5E14 to 5E15 ions/cm². If the dopant ions are a p-type, BF₂ ions canbe used under the condition that energy is in a range betweenapproximately 1 to 3 KeV and a dosage in a range between approximately1E14 to E15 ions/cm². The dopant ions can be implanted into the exposedactive region of semiconductor substrate 200 to form a low-concentrationdopant ion implantation region. The low-concentration dopant ionimplantation region becomes LDD region 204 through a subsequentannealing process. Meaning, LDD region 204 can be formed in the surfaceof the active region located at both sidewalls of gate electrode 203.

Subsequently, an insulating film can be deposited using a low-pressurechemical vapor deposition (LPCVD) method. At this time, the insulatingfilm can be composed of a three-layer laminate film having anoxide-nitride-oxide (ONO) structure including first oxide film 205,nitride film 206 and second oxide film 207. The thickness of first oxidefilm 205 can be in a range between approximately 150 to 200 Angstrom.The thickness of the nitride film 206 can be in a range betweenapproximately 150 to 200 Angstrom. The thickness of second oxide film207 can be in a range between approximately 300 to 500 Angstrom. Firstoxide film 205 and second oxide film 207 can be composed of tetra ethylortho silicate (TEOS).

As illustrated in example FIG. 2B, once the ONO insulating film isformed, it can be etched using a dry etching process having ananisotropic etching characteristic, such as a reactive ion etching (RIE)process. The etching results in the formation of spacer 208 having anONO insulating film configuration that remains on sidewalls of gateelectrode 203.

Source/drain region 209 may be formed in the surfaces of substrate 200at both sides of gate electrode 203 including spacer 208 using ahigh-concentration dopant ion implantation process. Particularly, ifn-type dopant ions are used, phosphorous P+ ions can be implanted intothe entire surface of substrate 200 at an energy range betweenapproximately 4 to 6 KeV and 4E14 to 5E15 ions/cm². If p-type dopantions are used, boron B+ ions can be implanted into the entire surface ofsubstrate 200 at an energy range between approximately 2 to 4 KeV and1E15 to 5E15 ions/cm². Under the above-described condition, thesource/drain region 209 is formed.

After formation of the transistor, a silicide layer can be formed onand/or over the entire surface of substrate 200 including source/drainregion 209 and gate electrode 203 of the transistor. In order to formthe silicide layer, a Co layer, a Ti layer and a TiN layer can besequentially laminated on and/or over substrate 200. The Co layer may beformed having a thickness range of between approximately 120 to 150Angstrom. The Ti layer may be formed with having a thickness range ofbetween approximately 190 to 210 Angstrom. The TiN layer may be formedhaving a thickness range of between approximately 210 to 230 Angstrom.The Ti layer can be used as a protective film against oxygen during areaction between Co and Si. The Ti layer may also control the reactionbetween Co and Si. The processes of forming the Ti layer and the TiNlayer may be continuously performed in the same deposition chamber ormay be separately performed in different deposition chambers.

After formation of the silicide layer, a first rapid thermal process(RTP) can be performed with respect to the resultant material. A CoSilayer can be selectively formed on and/or over the surface ofsource/drain region 209 and gate electrode 203. The first RTP may beperformed at a temperature range between approximately 450 to 500° C.for 50 to 60 seconds. Subsequently, after the first RTP is completed,the non reacted Co layer, Ti layer and TiN layer are sequentiallyremoved. At this time, the non reacted Co layer and the Ti layer can beremoved using a predetermined wet etching process.

As illustrated in example FIG. 2C, a second RTP can then be performedwith the resultant material. Cobalt silicide layer 210 can beselectively formed on and/or over the surface of source/drain region 209and gate electrode 203. At this time, the second RTP may be performed ata temperature range between approximately of 800 to 850° C. for 10 to 40seconds.

As illustrated in example FIG. 2D, a process of removing uppermostsecond oxide film 207 from spacer 208 having the ONO structure can beperformed. At this time, a wet etching process can be performed usingany one of a mixed solution of NH₄F and HF and a buffered HF solutionfor 30 to 60 seconds such that second oxide film 207 can be removed.

When the process of removing second oxide film of the ONO structure isperformed, contact stop layer 211 can be formed closer to a channelregion located at the lower side of substrate 200. Accordingly, largerstresses may be induced to the channel region.

As illustrated in example FIG. 2E, contact stop layer 211 can be formedon and/or over the entire surface of substrate 200 including gateelectrode 203 using a nitride film (SiN). Contact stop layer 211 can beformed using a plasma enhanced chemical vapor deposition (PECVD) method.Contact stop layer 211 may be formed having a thickness range ofapproximately of 300 to 500 Angstrom. The PECVD method can be performedat a temperature range of between approximately of 300 to 500° C. for 30to 60 seconds. The PECVD method for depositing contact stop layer 211can be performed using a bias power in a range between approximately 10to 20 W and whereby a ratio of SiH₄ to NH₃ is set to 3:1 to 5:1.

At this time, as the bias power is in a range between approximately 10to 12 W, SiN may exhibit larger tensile stress. As the percentage ofSiH₄ becomes larger than that of the NH₃, i.e., when the ratio of SiH₄to NH₃ is 5:1, larger tensile stresses can be obtained. In order toobtain larger tensile stresses, the transistor can be an NMOStransistor.

As the bias power increases to 18 to 20 W, SiN exhibits greatercompressive stresses. As the percentage of SiH₄ becomes smaller thanthat of the NH₃, i.e., when the ratio of SiH₄ to NH₃ is 3:1, greatercompressive stresses can be obtained. In order to obtain the largercompressive stresses, the transistor can be a PMOS transistor.

In accordance with embodiments, the MOSFET transistor can be an NMOStransistor. After the formation of the transistor is completed, contactstop layer 211 having a large tensile stress characteristic can beformed on and/or over the entire surface of substrate 200 including gateelectrode 203. Contact stop layer 211 can be deposited under thecondition that the bias power decreases and the percentage of SiH₄increases such that contact stop layer 211 exhibits high tensilestresses. In the process of forming contact stop layer 211, the latticedistance of the channel region may increase by also applying tensilestresses 212 to the channel region of silicon substrate 200. When thelattice distance of the channel region of the NMOS increases, electronscattering due to the lattice can be reduced and electron mobility canbe enhanced.

If the transistor is a PMOS, contact stop layer 211 can be formed onand/or over the entire surface of substrate 200 including gate electrode203 after formation of the transistor. Contact stop layer 211 can bedeposited under the condition that bias power increases and thepercentage of SiH₄ decreases such that contact stop layer 211 has therequired compressive stress characteristic. In the process of formingthe contact stop layer 211, the lattice distance of the channel regionmay decrease by also applying compressive stresses to the channel regionof silicon substrate 200. When the lattice distance of the channelregion of the PMOS decreases, electron mobility can be enhanced.

In accordance with embodiments, second oxide film 207 can be removedfrom spacer 208 having the ONO structure such that contact stop layer211 can be formed closer to the channel region. Accordingly, largerstresses can be induced to the channel region, and thus, electronmobility and the drive current Idr of the transistor may increase.

In accordance with embodiments, since electron mobility can be increasedby increasing applied stresses to a channel region of a transistor, itmay be possible to enhance the operability and electricalcharacteristics of a semiconductor device.

In accordance with embodiments, stress may be applied to a channelregion located at the lower side of a substrate by laminating a contactstop layer having a high tensile stress characteristic on and/or overthe entire surface of a substrate including a gate electrode afterformation of a transistor. This confirguration can enhance electronmobility in the channel region of the substrate. Consequently, the drivecurrent of the transistor can increase in addition to the operabilityand electrical characteristics of a semiconductor device.

Although embodiments have been described herein, it should be understoodthat numerous other modifications and embodiments can be devised bythose skilled in the art that will fall within the spirit and scope ofthe principles of this disclosure. More particularly, various variationsand modifications are possible in the component parts and/orarrangements of the subject combination arrangement within the scope ofthe disclosure, the drawings and the appended claims. In addition tovariations and modifications in the component parts and/or arrangements,alternative uses will also be apparent to those skilled in the art.

1-13. (canceled)
 14. An apparatus comprising: a semiconductor substrate;a transistor formed over the semiconductor substrate, the transistorincluding a gate electrode, a source/drain region and a spacer having alaminated structure on sidewalls of the gate electrode including atleast one first oxide film and a nitride film; a silicide formed overthe gate electrode and the source/drain region; and a contact stop layerformed over the entire surface of the substrate including the gateelectrode.
 15. The apparatus of claim 14, wherein the source/drainregion is formed over the surface of the substrate at both sides of thegate electrode.
 16. The apparatus of claim 14, wherein the silicidelayer comprises cobalt silicide.
 17. The apparatus of claim 14, furthercomprising a device isolation film formed in a field region of thesemiconductor substrate to define an active region in semiconductorsubstrate.
 18. The apparatus of claim 14, wherein the device isolationfilm is formed using shallow trench isolation (STI).
 19. The apparatusof claim 14, wherein the semiconductor substrate comprises at least oneof a conductive n-type and a p-type single crystal silicon substrate.20. The apparatus of claim 14, wherein the contact stop layer comprisesnitride having a thickness range of between approximately 300 to 500Angstroms.